The present invention relates to a one-chip semiconductor device in which circuit elements of a peripheral circuit such as a logic circuit are integrated on one chip together with a nonvolatile memory-cell array, and also relates to a method of manufacturing the semiconductor device.
In most one-chip semiconductor devices having a nonvolatile memory-cell array, the similar wiring structure is used in the memory-cell array region and the other region for circuits other than the memory-cell array (hereinafter referred to as xe2x80x9cperipheral circuitsxe2x80x9d) such as cell array driver circuits formed around the memory-cell array, logic circuits and SRAMs both formed around the cell-array driver circuits.
In the nonvolatile memories developed hitherto, one metal wiring layer or two metal wiring layers are provided in the memory-cell array region. The wires of the uppermost layer provided on the memory-cell array region have been finely patterned in accordance with design rules. These wires cause stepped portions of a passivation film formed on the wires. Thus, so called step coverage of the passivation film, i.e., protection film formed on the wires of the uppermost layer, is inevitably diminished.
FIG. 11 is a sectional view of a conventional nonvolatile memory device in which a two-layer wiring structure is used in both the memory-cell array region MR and the peripheral circuit region PR. A memory-cell array having nonvolatile memory cells MC is formed in the memory-cell array region MR of the silicon substrate 1. Each of the memory cells MC has a floating gate FG and a control gate CG. Peripheral circuits are formed in the peripheral circuit region PR. Each peripheral circuit comprises MOS transistors Q of ordinary type, each having a source S, a drain D and a gate G.
As shown in FIG. 11, a first interlayer insulating film 2 is formed on the silicon substrate 1 and covers the memory cells MC and the MOS transistors Q. First-layer wires 3 are formed on the upper surface of the first interlayer insulating film 2. A second interlayer insulating film 4 is provided on the first interlayer insulating film 2 and covers the first-layer wires 3. Second-layer wires 5 are formed on the second interlayer insulating film 4. A passivation film 6 acting as a protection film is formed on the second interlayer insulating film 4 and covers the second-layer wires 5.
Contact metal such as tungsten are filled in via holes formed in the first interlayer insulating film 2 so that n+ regions formed in the surface of the silicon substrate 1 and the first-layer wires 3 are connected with each other by contacts 17. Further, via holes are formed to provide contacts 17 between the first-layer wires 3 and the second-layer wires 5 as shown in FIG. 11.
As in most nonvolatile memories, the passivation film 6 is a silicon nitride film (hereinafter referred to as xe2x80x9cplasma nitride filmxe2x80x9d) formed by means of plasma CVD method. The plasma nitride film 6 hardly allows passage of moisture, hydrogen or impurities such as positive mobile ions. However, this nitride film 6 is inferior to TEOS (Tetraethyloxysilane) film and SOG (Spin-On-Glass) film in terms of the step coverage. If the second-layer wires 5 are arranged at a short pitch of, for example, 0.4 micron line and space, the passivation film 6 will have thin portions 7 and voids 8 at the step portions between second-layer wires 5 as is illustrated in FIG. 11. Each thin portion 7 formed at a step defined by a side of a wire 5 and the upper surface of the second interlayer insulating film 4 will fail to function as a passivation film perfectly. Mobile impurity ions such as sodium and humidity may pass through the thin portions 7 and first and second interlayer insulating films 2 and 4 from outside into the memory-cell array. This would lower the reliability of the memory-cell array, for example, endurance characteristics and data retention characteristics. The voids 8 are likely to hold contaminant including humidity and impurities during the manufacture of the nonvolatile memory device. If held in the voids 8, the impurities and humidity included in the contaminant will adversely influence the memory-cell array.
Mobile impurity ions, hydrogen and humidity may enter the memory-cell array, in such a small amount that they would make no problems in ordinary MOS transistor circuits. Even if they exist in so small an amount, they will likely destroy data in the memory-cell array after the nonvolatile memory device has delivered to the user.
The memory device shown in FIG. 11 may be a NOR-type flash memory device. If so, the first-layer wires 3 are used as bit lines in the memory-cell array region MR, while the second-layer wires 5 are used as wires backing word lines or bit lines or used as subsidiary wires for split signal lines of a word-line decoder or for the split bit lines.
If the second-layer wire 5 is used as word-line backing wire, each wire 5 may be used for one word line or a plurality of word lines. In the case where each wire 5 backs one word line, the wires 5 must be arranged at a short pitch. If so, the passivation film 6 will have many defects due to the degraded step coverage. Even if the pitch is relatively long, the step coverage of the passivation film 6 is insufficient at either side (i.e., step portion) of each wire 5. Consequently, mobile impurity ions and humidity will pass through the defects formed in the passivation film 6, eventually entering the memory-cell array.
As mentioned above, the similar wiring structure is used in the uppermost metal wiring layer of memory-cell array region MR and peripheral circuit region PR of the conventional nonvolatile memory device shown in FIG. 11. Therefore, the passivation film 6, i.e., the uppermost layer of the memory device, has defects, inevitably lowering the reliability of the memory-cell array. A decrease in the reliability of the cell array must be prevented. To this end, an insulating film may be formed on the second interlayer insulating film 4, covering the second-layer wires 5 and having a flat upper surface, and the passivation film 6 may be formed on the upper surface of the insulating film. This results, however, in an increase in the number of manufacturing steps and, hence, an increase in cost.
In the conventional nonvolatile memory device, metal wires are provided above the memory-cell array. The metal wires block the ultraviolet rays applied to neutralize the memory cells. The greater the number of layers of wires provided, and the shorter the pitch at which the wires of each layer are arranged, the longer the time required to neutralize the memory-cell array.
Further, the greater the number of wires provided above the memory-cell array, the greater the charging damage affected to the nonvolatile memory cells in the process of manufacturing the nonvolatile memory device. The charging damage results from discharge of high-voltage static electricity that is generated during the wire forming process. Hence, the greater the number of layers of wires provided above the memory-cell array, the larger the charging damage.
The present invention has been made in view of the above and has its object to provide a semiconductor device capable of being made at minimum cost and in which the wiring structure is improved to enhance the reliability of the memory-cell array. Another object of the invention is to provide a method of manufacturing the semiconductor memory device.
According to the first aspect of the present invention, there is provided a semiconductor memory device which comprises:
a semiconductor substrate having a first region and a second region located adjacent to the first region;
a memory-cell array including a plurality of nonvolatile memory cells provided in the first region of the semiconductor substrate;
a peripheral circuit formed of circuit elements other than the nonvolatile memory cells and provided in the second region of the semiconductor substrate; and
a multi-layered wiring structure including a plurality of interlayer insulating films, one located above another, for covering the memory-cell array and the circuit elements, and a plurality of layers of wires provided in the interlayer insulating films, wherein the layers of wires include an m number of layers of wires located in regions of the interlayer insulating films corresponding to the first region of the semiconductor substrate, and an n number of layers of wires located in regions of the interlayer insulating films corresponding to the second region of the semiconductor substrate, where n greater than m.
According to the second aspect of the invention, there is provided a semiconductor memory device which comprises:
a semiconductor substrate having a first region and a second region located adjacent to the first region;
a memory-cell array including a plurality of nonvolatile memory cells provided in the first region of the semiconductor substrate;
a peripheral circuit including circuit elements other than the nonvolatile memory cells and provided in the second region of the semiconductor substrate;
a multi-layered wiring structure including a plurality of interlayer insulating films, one located above another, for covering the memory-cell array and the circuit elements, and a plurality of layers of wires provided in the interlayer insulating films, wherein the layers of wires include an m number of layers of wires located in regions of the interlayer insulating films corresponding to the first region of the semiconductor substrate, and an n number of layers of wires located in regions of the interlayer insulating films corresponding to the second region of the semiconductor substrate, where n greater than m; and
a passivation film provided on an uppermost film of the interlayer insulating films, which has a part having a substantially flat body laying above the first region of the semiconductor substrate in which the m layers of the wires are located.
In the semiconductor memory device according to the second aspect of the present invention, the signal lines may be metal wires, and the passivation film may include a plurality of layers, at least the uppermost of the layers being a silicon nitride film formed by means of a plasma CVD method. Further, in a preferred embodiment of the present invention, a surface of the uppermost interlayer insulation film laying beneath the passivation film is provided with a SiH4 plasma CVD film having a flat surface with no contact hole.
The memory device according to the second aspect may further comprise a plate electrode located beneath a part of the passivation film which lies in the first region. The plate electrode is made of the same material as the signal lines of at least one layer provided in the second region and located above the m-th layer of signal lines, and covering the memory-cell array. In this case, the plate electrode may be connected to at least one terminal provided in the first region of the semiconductor substrate.
In the memory device according to the second aspect, the memory-cell array has a memory-cell array body storing data and a reference memory-cell array for imparting a threshold value to the memory cells included in the memory-cell array body. Further, the plate electrode is located above only a part of the memory-cell array in which the memory-cell array body is provided.
According to the third aspect of this invention, there is provided a method of manufacturing a semiconductor memory device which comprises:
forming a memory-cell array and circuit elements other than the memory cells on a semiconductor substrate, the memory-cell array comprising a plurality of nonvolatile memory cells;
forming a plurality of interlayer insulating films, one located above another, each covering the memory-cell array and the circuit elements;
forming an m number of layers of signal lines, on the respective interlayer insulating films covering the memory-cell array;
forming an n number of layers of signal lines, on the respective interlayer insulating films covering the circuit elements other than the memory-cell array, where n greater than m; and
forming a passivation film on the uppermost of the interlayer insulating films, which has a substantially flat upper surface lying above the memory-cell array.
In the method, an interlayer insulating film having the substantially flat upper surface may be deposited on an m-th signal-line layer covering the memory-cell array and the circuit elements. Then, after at least one signal-line layer is deposited above the m-th signal-line layer, a part of the at least one signal-line layer which lies above the circuit elements is patterned to form an n-th layer signal lines, leaving the remaining part as a plate electrode which covers the memory-cell array.
The method may further comprise applying ultraviolet rays to the memory-cell array, thereby neutralizing the memory-cell array, before the at least one signal-line layer is deposited.
In the present invention, fewer layers of signal lines are provided in the memory-cell array region than in the peripheral circuit region. The interlayer insulating film, on which the signal lines of the uppermost layer are provided in the peripheral circuit region, is processed to have a flat upper surface. This interlayer insulating film covers the signal lines of the uppermost layer provided in the memory-cell array region. Hence, that part of the passivation film, which lies above the memory-cell array region, is deposited on a flat surface. As a result, this part of the passivation film is sufficiently thick and has no defects such as voids or the like, even if the passivation film is one having insufficient step coverage, such as a plasma nitride film. The passivation film can prevents the memory-cell array from deteriorating in terms of reliability. Since no signal wires of the uppermost layer are provided above the memory-cell array region, the memory cells can be initialized within a shorter time than otherwise, by application of ultraviolet rays.
Having more layers of signal lines than the memory-cell array, the peripheral circuit can have high integration density and can operate at high speed.
In the process of forming the signal lines of the uppermost layer, that part of a metal film, which lies above the memory-cell array region, is not patterned into signal wires. This part of the metal film is used as a plate electrode, which covers the memory-cell array and effectively prevents contaminant such as impurities and humidity from entering the memory-cell array. The plate electrode needs not be made of the same material as the signal lines of the uppermost layer, which are provided in the peripheral circuit region. It only needs to be located above the uppermost layer of signal lines provided in the region of the memory-cell array.
Once the plate electrode has been formed above the memory-cell array region, it is no longer easy to neutralize or initialize the memory-cell array by applying ultraviolet rays to the array. Nonetheless, if the memory cells are electrically erasable programmable ones, it suffices to apply ultraviolet rays to the reference memory-cell array which generates a threshold value for data programming. Hence, the plate electrode may be provided over the body region of the memory-cell array only, not above the reference memory-cell array.
As mentioned above, it no longer easy to apply ultraviolet rays to the memory-cell array once the plate electrode has been formed. To neutralize (or initialize) the memory-cell array, it is desired that ultraviolet rays be applied immediately before the film to be processed into the plate electrode and the signal lines, is deposited on the uppermost interlayer insulating film.
The plate electrode may be electrically connected to the substrate in which the memory cells are formed or to a terminal made of a diffusion layer provided in a well. The plate electrode therefore protects the memory cells from charging damage which will occurs when wires are formed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.